1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices and, more particularly, to the fabrication of semiconductor integrated circuit chips provided with a means of stopping propagation of interface de-lamination between dielectric layers originated from the wafer dicing process.
2. Description of the Prior Art
Semiconductor manufacturers have been shrinking transistor size in integrated circuits (IC) to improve chip performance. This has resulted in increased speed and device density. For sub-micron technology, the RC delay becomes the dominant factor. To facilitate further improvements, semiconductor IC manufacturers have been forced to resort to new materials utilized to reduce the RC delay by either lowering the interconnect wire resistance, or by reducing the capacitance of the inter-layer dielectric (ILD). A significant improvement was achieved by replacing the aluminum (Al) interconnects with copper, which has ˜30% lower resistivity than that of Al. Further advances are facilitated by the change of the low-k dielectric materials.
However, one shortcoming associated with the use of low-k dielectrics is that almost all low-k dielectric materials possess relatively lower mechanical strength than that of conventional silicon oxide dielectrics such as FSG or USG. The use of low-k dielectrics poses this industry another problem that the adhesion ability, either at the interface between two adjacent low-k dielectric layers or at the interface between a low-k dielectric layer and a dissimilar dielectric layer, is inadequate to meet the requirements in the subsequent wafer treatment processes such as wafer dicing, which is typically performed to mechanically cut a semiconductor wafer into a number of individual IC chips.
It has been found that the so-called “interface de-lamination” phenomenon occurs between low-k dielectric layers during or after the wafer dicing process is performed, causing performance degradation of the IC chips. In light of the above, a need exists in this industry to provide a solution to the undesired propagation of the interface de-lamination between low-k dielectric layers originated from the wafer dicing process.